While attachment methods have increased performance in backplane connectors, manufacturability, reliability, and repairability remain critical design considerations.
By Phil Stokoe and Burke Hunsaker
It is well documented that launching of high-speed, high-density signals into and out of a printed circuit board’s inner layers is a significant challenge for electrical performance and interconnect density. Over the last decade, electronic product designs using press-fit technology have continued to drive for faster data rates, increased signal densities, and expanded functionality in the same box. To stay ahead of the increasing needs of electronic products, backplane connector manufactures have continued miniaturizing the compliant pin from a diameter of 1.0 mm to the present 0.35 mm.
With widespread availability of semiconductor devices capable of driving high gigabit-per-second signals over longer PCB traces, system designers are presently considering product designs with data rates up to 25 Gbit/s. This requirement, coupled with increasing signal densities and the push to reduce PCB layers, strongly indicates that continued diameter reduction of the PCB through-via will challenge the physical capabilities of compliant-pin miniaturization.
The good news is that significant advances in backplane connectors using a surface-mount footprint have proven reliable and repairable. An optimized surface-mount pad footprint and via structure that minimizes adverse via launch effects on signal integrity provides system designers an interconnect technology capable of expanding with their future system requirements. However, to successfully implement a surface-mount backplane connector, several process challenges must be considered, including connector lead geometry and coplanarity, connector-to-PCB registration, reflow solderability, solder-joint reliability, and connector repair.
Successful attachment
Lead coplanarity presents the largest challenge in attaching surface-mount backplane connectors. This is based on the fundamental principle that the leads must be in intimate contact with the solder paste after any solder slumping or stencil variation. Assuming the use of an industry-standard 6-mil stencil that typically yields a solder deposit between 7 and 8 mils in height, and the leads are in intimate contact with the paste, the coplanarity of the connector must be less than 6 mils when used with a perfectly flat PCB. Taking typical PCB warping into account, which IPC-6012 limits to 0.75% for PCBs with surface-mount components, the coplanarity issue becomes insurmountable. For example, a typical 10"-long backplane connector built with the present coplanarity methodologies could not be attached reliably to a 10"-long PCB exhibiting the maximum warp.
The traditional approach to overcoming the coplanarity challenge was to keep all parts of the connector as rigid and straight as possible, minimizing any deflection and variation. This approach works well for small-footprint connectors, but as the connector footprint grows, so does the difficulty in maintaining rigidity and minimizing variation. An alternative solution to this coplanarity problem is to design the connector to be conformal instead of rigid. This approach allows the connector to be “fitted” or conformed to the PCB surface using simple fixturing methods. To accomplish this, the conformity of the connector is divided into wafers comprised of single rows of leads, where the coplanarity of the leads can be controlled within a range of 2 mils. These wafers are linked together using a conformal organizer. When the connector is fixtured onto the board, the organizer allows for small (on the order of 1 mil) relative motion between sets of wafers, ensuring that all the solder leads are in intimate contact with the solder paste.
To place a surface-mount backplane connector correctly onto the PCB, features must be designed into the connector and the accompanying PCB footprint that allow for acceptable lead-to-pad registration and the placement of the connector. (Today this is a manual process, but future pick-and-place machinery must also be considered.) One approach is to use a set of alignment holes in the PCB and guide pins in the connector itself, integrated with front and rear organizers, which accurately maintain the lead-to-pad X-Y registration. The holes must be sized and located such that the connector is not over constrained onto the PCB, especially during reflow where the thermal expansion differentials are at a maximum. Using a set of slotted and round holes on the PCB and corresponding guide pins on the connector allows for repeatable, accurate placement of a typical-sized backplane connector.
Repeatable reliability
The consistent formation of acceptable solder joints, or solderability, at all locations of large array connectors is another processing challenge. Solder-joint failures can be grouped into two broad categories: opens (no electrical connection) and shorts (undesired connections). The occurrence of opens is in large part due to the poor coplanarity of the solder leads, resulting in non-intimate contact with the solder paste. The occurrence of shorts is determined by the connector lead spacing and the amount of solder deposited onto the PCB pads. As the density of connectors increases, the spacing of the leads decreases, thus increasing the likelihood of shorting. A novel approach to mitigate shorting in the connector design is achieved by creating a footprint pattern which uses surface energy to draw excess solder away from potential shorting sites. Applying solder paste to only certain areas of the PCB pad and leaving other areas of the pads free of paste creates a scenario where the solder paste will migrate in a pre-determined direction as the paste wets the remaining pad.
The size and corresponding thermal mass of the SMT connector presents a further challenge. Large temperature gradients occurring within the connector during the reflow process result in poorly formed solder joints, and in some cases no joints at all. This temperature gradient is further magnified when using “lead-free” process parameters. Standard multi-zone IR/convection and vapor phase reflow ovens have been used to gain insight into thermal gradients. The thermal profiles obtained from these tests showed that for the high-mass connectors, the high thermal transfer capability of vapor phase processing was required for the connectors and PCBs to be brought up to the specified temperature. For connector configurations with low mass, both IR and convection ovens provided acceptable thermal gradients.
A challenge for all SMT components is to create a robust and reliable solder joint. The overall reliability of the solder joint is affected by the coplanarity, registration, and solderability of the leads. In addition, solder-joint reliability is affected by the ability of the leads to absorb stress before the stress is transferred to the solder joint. The more rigid the lead, the more stress that lead transfers into the solder joint. To isolate this stress, a compliant lead can be used to shield the solder joint from transmitted stresses as the lead itself absorbs the stress. Creating bends in the lead transforms a rigid lead into a compliant lead that effectively protects the solder joint from stress.
Repairability
Connector repair remains a necessity in the compliant pin and SMT backplane industry for a variety of reasons, including initial attach failures and “in-use” damage. There are two mainstream approaches to terminated connector repair. The first and most common is the removal and replacement of the entire connector, while the second is the replacement of only the “bad” components. For compliant pin applications, the established approach involves the use of strictly mechanical means to extract and repress the connector as a whole, or in parts.
Increasing use of high-speed SMT terminations for very large lead arrays has forced the rethinking of connector repair. Where feasible in small I/O applications, replacement of the entire connector is a viable approach; nonetheless, added variables enter the process as thermal stresses, alignment, solder application, and chemistry cloud the solutions. The recent lead-free initiatives have also placed further burdens on the process with the requirement of higher temperatures.
 FIGURE 1. Using industry-standard equipment, an SMT daughtercard rework nozzle assembly performs selective repair of a 100-wafer, 1,400-I/O connector. |
New connector design approaches allow SMT repair within the “waferized” connector (see Fig. 1). This modularized design on both halves of the connector also allows an alternative selective approach to whole connector replacement. This new approach saves the OEM money in its ability to only replace the bad wafers without the need to replace the entire connector. When connector wafer counts exceed 50 wafers, this advantage really shows its merits. Although this modularity allows the easy customization of connector configurations without re-tooling, it results in unique repair challenges in the form of standardizing tooling and process solutions (see Fig. 2).
 FIGURE 2. Single-wafer modularity, like that of the Ventura waferized eight-row backplane SMT header, allows custom connector configuration without the need for re-tooling. |
A successful implementation of a modular repair process addresses site dressing, solder application, and alignment. Advantages to SMT termination repair include maintaining both mechanical and signal integrity, and the ability to do multiple repairs on the same site. However, consideration must be given to the connector design and its associated repair tooling and processes.
The elimination of both compliant-pin and SMT connector repair does not seem likely due to the inevitability of damage and termination process deficiencies. In addition, the shift from compliant-pin to SMT-style terminations is forecast to increase with application speeds and system density. These factors will continue to force system designers to consider the “repairability” of the proposed design solution.
ACKNOWLEDGMENT
The authors would like to acknowledge Joe George for help on the article.
PHIL STOKOE is manager, product development engineering, and BURKE HUNSAKER is a development engineer at Amphenol TCS, 44 Simon Street, Nashua, NH 03060. Tel: (603) 879-3000; Email: Phil.Stokoe@teradyne.com.
