San Jose, CA - Interconnect designer SiliconPipe has formally announced a new high-speed interconnect design with no package vias. The “StairStep” high-performance ball-grid-array (BGA) integrated-circuit (IC) package design offers designers a quick and easily implemented solution to high-speed signal integrity. The use of the package can be accomplished using existing manufacturing techniques, with little or no modification. The company is offering licensing opportunities on the interconnect design.
The new StairStep package is a high-performance, low-cost substrate solution that uses tiers of “stair-stepped” contacts at the package edges (see Fig. 1). This design sequentially exposes the interconnection layers of redistributed circuit connections with no vias or stubs. It adds many advantages beyond traditional PGA packages. The package addresses the I/O density problem along with providing significant performance and reliability improvements, all while reducing the manufacturing cost.
 FIGURE 1. The StairStep interconnect design uses layers of stair-stepped contacts at the package edges to eliminate plated vias. |
“Most engineers involved in high-speed digital design understand that the connections, or transition regions, in a circuit cause many difficulties. Thin, coplanar structures are good for high-speed systems, because thin structures minimize the size and bulk of these transition regions, improving transmission-line impedance control and also crosstalk. At high speeds, thin structures look good to me, and this is such a structure,” says Dr. Howard Johnson, the author of High-Speed Digital Design: A Handbook of Black Magic, the Signal Integrity columnist for EDN magazine, and a frequent guest lecturer at Oxford University.
Cost savings
In the new design, the cost savings are realized due to the reduction in the number of manufacturing steps and especially the elimination of plated vias. The improved, simpler structural elements of the package allow for higher manufacturing yields. The design requires no drilling or plating, resulting in fewer steps-a 100% savings in the costs associated with via processing. The design also reduces or eliminates electrical testing costs. Because the package uses individual layers, each layer can be inventoried and used to create custom packages, including mixed-pitch I/O if desired, on a moment’s notice. The design costs are also reduced significantly. Signal layers are directly converted to micro-strip or stripline through added metallization, meaning signal-integrity tools or experts are reduced or eliminated. Less material used in the design equates to a 30% savings in material cost.
Elimination of plated vias enhances the performance, further reduces cost and routing space, and improves signal performance issues, such as crosstalk, impedance variation, and reliability. Using the StairStep package, differential pairs, common in high-speed circuit design, can be designed for virtually zero skew, while crosstalk can be nearly eliminated. The package offers designers a clear channel, allowing for lower voltages for signal transmission. The designer has the opportunity to design internal I/O terminations. Via-related impedance and crosstalk are eliminated. This means zero impedance change, and zero via crosstalk.
Reliability is the key to success with this package. One obvious improvement comes from the elimination of the plated vias. This means a 0-ppm via defect rate.
“The Achilles heel of high-speed design-plated vias-have been eliminated with our new StairStep package,” comments Kevin Grundy, president and CEO of SiliconPipe. “Having a clean channel means better signal integrity, while using lower voltages results in less power requirements.”
Because the StairStep package uses current materials and manufacturing techniques, such as flex or rigid material, optical inspection for electrical performance is possible with existing test probes. The package uses an all-lithographic process with no serial drilling needed.
