Flexible circuits and dual-path interconnects can be readily implemented to create high-speed, low-power electrical channels without costly disruptions to manufacturing infrastructures.
By Joseph Fjelstad, Kevin Grundy, and Gary Yasumura
Low-power electronic systems using less than 2% of specified power, and memory modules that break the long-standing memory-performance bottleneck are not fantasies. Real possibilities can be gained with a thorough reexamination of the electronic interconnection architecture and a reconsideration of both electronic connector design and how they are used. Framing these opportunities in light of examples gives an appropriate background to fully understand these low-power memory solutions.
Stringent cost restrictions make it increasingly difficult to satisfy the performance demands placed on electronic products and systems. While in the past the problem could be segmented and dealt with piecemeal to meet cost and performance needs, it is clear that this approach has a limited future.
In fact, the matter of performance is now intrinsically linked to cost. Adjusting a single element of the interconnection hierarchy is no longer cost effective. Instead, to more effectively meet the challenge, all elements of an electronic assembly must now share the burden of providing a viable performance-capable path for high-performance electronic signals. Moreover, all interconnection elements in an electronic system must be designed mindful of all of the interconnection elements that precede and follow it.
However, the challenge of getting all elements of the interconnection hierarchy to work together in such a manner is daunting at best because change is anathema to design and manufacturing. There is substantial vested interest in the familiar solutions of today. Unfortunately, the old solutions have limited ability to make the journey to the future and thus new devices and methods must be found and adopted. Connectors are one of the critical links of the electronic interconnection chain and a good demonstration platform for making the case.
Connectors are pivotal elements in the electronic signal path. While recent significant improvements have improved connector performance, the interconnection pathways that precede and follow the connector often limit the full benefit of the connector. For example, in the realm of high-performance or high-speed signal transmission, the fundamental challenge is signal integrity. Signal integrity is best summarized as the degree to which a digital signal represents a 1 or a 0 at the receiver.
Proper design
The basic problem is that no matter how good the connector is, it cannot improve the quality of the signal that precedes or follows it in the electrical path. Fortunately the connector need not remain locked in place as an impotent passive interconnection device. In fact, with proper connector design, the connector can influence and actually lead the system design process because of its pivotal nature. A few examples make the case.
In a typical PCB design, distributed signals must compete for routing channels. Because numerous signals of varying strength and proximity travel through a PCB, a substantial coupling translates to noise that unfortunately obscures the signal. Degradation of signal integrity makes it more difficult to determine if the value sent was in fact a 1 or a 0. Minute changes in a transmission line’s impedance, caused by tiny defects created by improperly designed interconnections, space reductions, and various capacitive stubs, also generate noise due to signal reflections. These create waveform distortions and signal skew caused by unequal signal lengths for clocked circuits.
Although stringent design practices can partially control the noise in a given interconnection substrate design, a host of vexing nits in the system intrinsic to PCB manufacturing always remain. These signal disrupters include inconsistencies in dielectric properties, inconsistencies in trace width such as “mouse bites” or neck downs, dielectric loss, conductor loss, stray capacitance, variation in circuit spacing, uneven copper thickness, and adhesion treatments, among others. And then, of course, there are the matters of reflections due to electronic stubs from connector contacts and circuit features such as plated vias. The net effect of this complex web of interactive elements is that they make it extremely difficult to predict and design for reliable high performance.
There is a way out of the maze. The fundamental solution is conceptually simple: route the highest speed signals between chips using a more direct path. The preferable path is through controlled-impedance channels established in all three dimensions of circuit space. The medium best suited to this at present is a flexible circuit. In practice, the flexible circuit is connected to the top of an IC package, which has high-speed interconnection points exiting the package on the upper surface. From there, the flex circuit is connected directly to a communicating element which could be another chip, a PCB, or a connector.
When making high-speed interconnections directly between chips and the connector, some modification of the connector is required. However, the benefits are significant. Segregating the high-speed interconnections and routing them separately in materials that can be easily controlled, such as through flexible cables that route from the upper surface of the package directly to the connector, breaks through the signal integrity management logjam. Routing through flex cables solves the problem in a fundamental, easily manufactured, and managed way.
This patent-pending method has been demonstrated in the laboratory with impressive results. The high-speed, low-power proof-of-concept system was retrofitted with a 10-Gbit/s SERDES chip with a microstrip flex circuit mounted to the top of the IC package (see Fig. 1). Wire bonds were terminated on two, 10" differential-pair circuits on the flex circuit, positioned directly atop the bond pads of the existing package. The flex circuit was bifurcated and each of the two differential pairs was connected to a connector blade modified to allow for direct connection to the flex circuits (see Fig. 2). The connector blade was in turn connected to a 10" backplane, creating a 30" loop for the send and receive pairs on the SERDES chip.
 FIGURE 2. The fundamental elements of the structure simplify board design by removing complicated signal paths with multiple potential parasitic elements. |
The demonstration system had surprising results. The Aeluros AEL1002 device used in the assembly is rated to transmit an 800 mVp-p signal across a 12" PCB with one connector. However, the demonstration vehicle proved the device’s channel efficiency provided enough signal integrity to more than double the operating distance with two connectors while simultaneously reducing voltage to 100 mVp-p-a power reduction of 64x (more than 98%). Furthermore, the system delivered a 60% timing margin at the receiver, using industry-standard non-return-to-zero (NRZ) signaling at a low signal voltage. More detailed testing is underway at the present time to ascertain full channel parameters and determine the upper limit of its performance.
Two pathways
Another area of electronics technology that could benefit from rethinking the structure of the connector is memory and the time-honored dual-inline memory module (DIMM). Unlike backplane connectors, which have significantly improved over time with respect to high-speed signals, the DIMM has languished, saddled with the burden of maintaining low cost and the perception that silicon-based solutions would be sufficiently adept at managing the problem. However, as successive generations of memory chips increase in native speed, the challenge of allowing them to live up to their performance potential will increasingly fall to the connectors used for memory modules.
In keeping with the concepts previously described, a new proprietary DIMM connector design is in development to engage the needs of future memory. The new connector, suited to the needs of the next-generation FB-DIMM modules, once again separates high speed from low speed by creating a path that allows high-speed connections to go directly between connected modules, while low-speed connections take traditional routing pathways through the PCB (see Fig. 3). This dual-interconnection structure and routing method effectively eliminate most of the parasitic effects associated with traditional memory connector designs, while holding the line on cost. In operation, the high-speed signals will generally be routed through the middle of the connector, which is the location of the advanced-memory-buffer chip required for next generation FB-DIMM memory modules to help meet performance goals.
In summary, electronic connectors will continue to reside on the critical path of electronic interconnections for the foreseeable future. In that position, they have a unique opportunity to play an influential role in determining the electrical signal pathways that both precede and follow them. Future projects are targeted to the development of low-cost, high-performance connectors suitable for both backplane and general applications.
JOSEPH FJELSTAD is founder, KEVIN GRUNDY is president and chief executive officer, and GARY YASUMURA is research & development engineer at SiliconPipe, 992 DeAnza Blvd., No. 201, San Jose, CA 95129. Tel: 408-973-1744; Email: jfjelstad@siliconpipe.com.
