By Valerie Coffey
In high-speed computer systems of 10 Gbit/s and beyond, unstable core voltages supplying the semiconductor are a fundamental performance limitation. System designers must concentrate more and more on optimizing both signal and power integrity as lithography shrinks, switching speeds rise, and power requirements increase. In response, researchers at Silicon Bandwidth (San Jose, CA), a system-level interconnect development company, presented a system-wide approach to signal integrity with a three-prong design platform last year (see Connector Specifier, April 2004, p. 10).
In a systematic fashion, literally, the same company unveiled their solution to the power integrity part of the equation at DesignCon 2005 in Santa Clara, CA, February 2, 2005. The traditional approach to maintaining core voltage stability and suppressing switching noise has been to provide adequate decoupling capacitance, but legacy and brute-force solutions have proven ineffective. These consequently limit microprocessor maximum operating frequency. Rather than crowding the PCBs and cards with discrete capacitors, Josh Nickel, research and development engineer at Silicon Bandwidth and adjunct professor of electrical engineering at Santa Clara University, presented a decoupling platform that integrates discrete or custom capacitance into the voltage core much closer to the die.
This so-called “CapCore” platform integrates core decoupling capacitance inside an interposer or socket. The most feasible and common implementation of CapCore involves discrete capacitors soldered between the core power and ground pins (see Fig.). They provide more proximal decoupling and suffer less loop inductance, making them far more effective to the power delivery. The interposer provides substrate solder attach on top and PCB solder attach on the bottom with formed pins.
 FIGURE.The “checkerboard” configuration of a CapCore prototype on a 1-mm pitch shows power and ground pins in the center surrounded by signal pins. |
Core power-supply pinouts vary from checkerboard patterns to random configurations. The checkerboard power-ground grid provides the closest possible ground return path and leads to the lowest loop inductance. The checkerboard configuration also readily lends itself to a dense array of packed capacitors.
“The prototype of this new configuration is only part of the solution,” emphasized Nickel. “It is the system-level value that is of paramount interest to the OEMs and end customers.”
Specifically, the relocation of hundreds of PCB decoupling capacitors from the PCB to the CapCore simplifies the PCB architecture, reduces layer count, and eliminates expensive high-density interconnect technology and related exotic via schemes. Along with each capacitor, two solder joints are removed, along with all the supporting pads, vias, and traces, reducing materials, assembly, and yield costs. The liberated PCB space simplifies routing, relaxes design rules, and simplifies layout.
CapCore might first appear as “just another parasitic interconnect;” the common euphemism being “increased inductance.” In fact, as Nickel elaborates, signal performance is compromised by mismatched impedance, not additional interposer height. Thus, CapCore provides coaxial signal options for improved bandwidth and reduced crosstalk. The interposer main body is a grounded, metallized plastic housing that isolates insulator-coated pins and provides a return path. Its signal performance therefore is height-independent.
Circuit model simulations of a 2.5 Gbit/s signal applied to a 2.7-mm trace-CapCore-trace interconnect showed that the impact of the extra solder ball required to mount the interposer had a minimal impact on signal performance. An ideal evaluation would involve system-level co-design and analysis with interested customers, says Nickel.
Reference
- J. Nickel, J. Rosenberger, DesignCon 2005 Proc., Track 5, Session WP1 (2005).
