A "holistic" system-wide approach to system design and three distinct design platforms form an integrated solution to connector bottlenecks.
By Stanford Crane and Josh Nickel
The connector industry is perhaps at its most interesting moment in history. Why? Because the sweeping changes in the electrical, mechanical, and thermal performance demands at the system level will render most of today's widely used connectors unusable before the decade's end.
It is increasingly evident that the era of compartmentalized system design and connector-as-commodity or afterthought is drawing to a close. The optimal development strategy, on the other hand, is now to integrate the connector supplier into the design and deployment ecosystem early in the product concept stage.
The origin of this change in strategy goes back to the semiconductor engine driving the electronics industry. Along with shrinking lithographies came both lower voltage levels and noise budgets. Today, signal integrity and power delivery within the system are of paramount importance. For the purchasing agent, simply browsing a catalog for a connector or socket of a particular pin-count has become dangerously simplistic.
How must companies contribute within this environment to become part of the solution? A more optimized approach for designers would be to consider a "holistic" methodology to address this challenge. The most successful solution assesses the problem from a system-wide perspective.
By combining several highly developed interconnect technologies, three distinct platforms emerge, all of which address the central cause of limited system performance: suboptimal interconnect signal integrity. This "trilogy" of platforms, deployed in combination, offers the end-user improved bandwidth, lower crosstalk, reduced jitter, and lower bit-error rates (BERs). Moreover, these technologies enable lower system cost by streamlining both structure and process.
From the architectural point of view, the system can only perform to its fullest potential if the various elements are in balance. For example, high-speed semiconductors are "choked" in their ability to transceive at the system level by slow connectors, slow sockets, or slow printed circuit boards (PCBs). These gating factors unbalance system components and limit performance. Unfortunately, the industry has lagged in its adoption of new interconnect technology, continuing to employ mechanically cumbersome sockets and obsolete packaging with only marginal performance advances.
Not only are new products needed, but new ways of doing business with suppliers and end-users are required as well. The wide scope of the R&D efforts necessitates a working relationship between the manufacturing infrastructures and knowledge-based delivery systems.
Last resorts
Certainly, OEMs and ODMs have attempted to compensate for the lack of such a unified solution. In desperation, designers have resorted to a series of "fixes" such as backdrilling problematic PCB via stubs, adding ever more passives (chiefly capacitors) to already densely populated PCBs, and the integration of exotic and expensive materials.
Furthermore, active signal-processing technologies such as adaptive equalization, pre-emphasis, repeaters, and even crosstalk cancellation have hopped aboard the performance bandwagon. All of these "fixes," however, are expensive remedies, which is counterproductive in an industry perpetually forced to reduce costs. Worse, they introduce adverse, unpredictable side effects with wide-ranging results.
Backdrilling is a widely used and relatively cheap manufacturing step, but backdrilled holes consume costly PCB real estate. For high-end boards, questions of yield arise, as highly populated boards are correspondingly more expensive.
As for passives, additional components translate to additional costs and complexity, further reducing reliability. Although active SI techniques increase data-rate performance, costly repeaters and signal conditioners consume space and introduce latency—both unacceptable. Although system designers increasingly rely upon signal conditioning, any improvement in the passive interconnects diminishes this reliance and complements existing actives.
Ultimately, the potential gains using backdrilling, passives, exotics, and actives are marginal, considered against yield losses, cost, and reliability. Performance limitation is a system-level problem requiring a new paradigm in connector design. Unfortunately, many design approaches begin with a myopic view of system performance. We need to step back and look at the entire system if we want to make advances.
Experts in signal integrity attest to the fact that approaching the problem as a system-wide challenge is the only way to make advances, not as an afterthought in the design and build sequence. The goal is to provide less sensitivity to process and design variations, and, just as important, to leave significant margins for next-generation systems. Instead of playing catch-up with the design process, it is far more profitable to design-in the system performance.
Often, technology adoption seems glacial. It might be said that the industry lacks vision, denying any pressing demand for quantum-leap advances. However, technology often presages the perception of need; demand itself grows with the deployment of a new technology, as evidenced in cell phones, the Internet, or even the automobile.
Where to begin
With the origin of the telephone, simple, inexpensive connector designs met the needs of a rapidly growing technology. Subsequent developments in electronics inherited these early connector designs, adapting them for increased density and mechanical reliability. As both signal integrity and PCB size became critical, system designers relied on costly "fixes" rather than attacking the problem at its roots. This lack of perspective led to reliable mechanical connectors, yet performance "dis-connectors."
System performance is like traffic or water flow. Highway lane reductions and sharp turns cause traffic congestion. Similarly, boulders and cascades introduce turbulence and snagging. In system performance terms, these difficulties translate to reduced bandwidth, lower data rates, higher noise and crosstalk, stricter design rules, and latency.
An ideal starting point for system performance improvement is at the backplane. Widely deployed in switches, routers, and servers, their structures interconnect with signals from various daughtercards, making the connector bandwidth critical.
 FIGURE 1. High-speed, high-density, surface-mount connector allows a right-angle backplane connection with a daughtercard (60 pins shown). |
Thus, the first platform is a high-speed, high-density surface-mount backplane connector that incorporates a mating interface comprised of four-pin clusters (see Fig. 1). The individual clusters consist of a central insulating buttress supporting four separate contacts attached at 90( intervals. This enables higher densities, low insertion forces (20 g per pin), and normal forces of 60 g per pin.
Because signal integrity is the principal concern, the connector is essentially an array of mated coaxial channels whose design allows it to function in both single-ended and differential configurations. The coaxial structure provides proximal current return-path continuity and consistent transmission-line cross-sections through the entire signal path. The mating interface retains this "coaxiality" with shielding and with a low-insertion-force ground contact for each pin.
The connector, including the PCB interfaces, permits remarkable bandwidth, with measured insertion loss of only -2 dB at 15 GHz, and reflection of -10 dB at 10 GHz. Most critical, crosstalk is an astonishing 0.8 % at 50 ps risetimes, a consequence of the ingenious coaxial design. Deployed in conjunction with the second technology of the Trilogy, we eliminate problematic PCB via stubs, and render the connector-PCB interface transparent to today's data rates and scalable to tomorrow's. Connector characterization and backplane performance tests demonstrate that spectacular advantages in signal integrity are realized.
The second platform
The second platform is a surface-mount-enabling, simplified process: partial-through-hole PCB technology. Its elegance and appeal arises from its simplicity. Holes are drilled only to the trace layer and remain as unplated "wells." Two interconnection approaches between the trace pad and the package, interposer, or connector above the PCB are possible. In the first, pins of variable length are inserted into the wells, and connect to their respective signal-routing layer and reflowed with solder inside the well. In the second, the well is filled with conductor, and the planarized PCB surface enables surface mounting.
Signal integrity improves radically with the removal of the plated-through-hole (PTH) stub. These stubs are well known detriments; they cause low-impedance reflection and inhibit transmission. The PTH via stub fields act as an array of interacting antennas, and have been identified as the dominant source of system crosstalk. Simulated and measured data confirm that removal of the stub and T-junction at the trace reduces the radial wave excitation and substantially lowers crosstalk. Improvements to system performance are obvious.
 FIGURE 3. The mated socket ("mezzanine connector") in this photomicrograph provides a high-speed 8-mm connection between the PCB and substrate/die on a 1.12-mm grid. |
Furthermore, simplification of signal path cross-section from package to via to trace reduces reflection and increases transmission. Measured data reveal lower reflection than existing via-in-pad and microvia technologies.
Most significantly, this platform lowers PCB layer count and reduces overall cost. It liberates the routing space consumed by PTHs and backdrilled holes beneath the traces, thereby enabling layer-count reduction, as demonstrated in several applications. Reduced process steps, standard manufacturing process, no plating, and less backdrilling together significantly reduce costs. Cost compilation by a PCB manufacturer shows 30% or greater reduction, compared to high-density-interconnect technologies applied to a high-end 26-layer server PCB.
High-speed socket
The third platform in the trilogy is a modular-type, high-speed, surface-mount mezzanine connector/socket technology (see Fig. 4). This versatile technology is adaptable to many applications, demanding superior signal integrity, lowered costs, improved contact reliability, significantly lower insertion force, and more efficient power delivery.
 FIGURE 4. The socket's 4-pin clusters, power/ground straps, and substrate/die are in the top layer above with solder balls below (insulating body shown transparent). |
Employed in conjunction with the previously described PCB technology, this combination, when fully integrated, offers the highest performance chip-to-board solution available. The configuration allows the implementation of a novel power delivery system consisting of power/ground "rails" or "straps." These are configurable for high switching current needs, replacing hundreds of power and ground pins, and liberating space within the socket under the substrate for capacitance.
The three design platforms, closely related in concept, work in concert to improve performance, simplify design flows, relax design rules, lower power requirements, liberate PCB real estate, and lower layer counts. From a "strictly business" standpoint, the trilogy reduces system cost and substantially improves performance.
System performance tests validate these technologies. The tests showed that, regardless of the channel parameters, the deterministic jitter and BER using the triology design were consistently lower than that in the legacy system—by two orders of magnitude, in some cases.
STANFORD CRANE is chief technical officer and JOSH NICKEL is a research and development engineer at Silicon Bandwidth, 2890 Zanker Road, Suite 102, San Jose, CA 95134. Tel: (408) 965-1260; email: scrane@silicon bandwidth.com, jnickel@siliconbandwidth.com.
