High-performance, low-cost interconnect systems begin at the design stage by optimizing connector slots, reducing backplane layer count, avoiding high-performance board materials, and scaling existing designs.
BY Richard Humphrey
Just a few years ago, as semiconductor manufacturers introduced devices running above 3 Gbit/s and system designers began pursuing the >1-Tbit/s chassis, design focus was on optimizing system cost, speed, and bandwidth. Today, the trend is to develop products that maximize the performance of existing systems with plenty of headroom for future upgrades while continuing to control system cost.
Achieving this balance presents several challenges such as time-to-market, planning for an upgrade path, and architecture choice. Often the tradeoffs made to lower system cost at the early design phase negatively impact the system's final cost and performance in its typical application. For example, many OEMs are currently designing in lower-cost off-the-shelf components with little regard for system upgrade paths or other hidden costs.
How does cost affect design? In a fully loaded system, the silicon, interconnect, and printed circuit boards (PCBs) compose as much as 70% of the total system cost. The chassis (metal, backplane, power, and cooling) make up the balance. Costs associated with manufacturability and scalability are less tangible but still important. Often, the chassis is the focus of cost reduction. Although that may reduce the entry barrier for prospective customers, total system cost is more critical for the acceptance of the product.
The choice of architecture presents major cost tradeoffs. In a star scheme, switch-fabric cards, designed to connect to multiple I/O cards, are typically redundant. The initial switch and unused I/O slots are useless until more I/O cards are added. Compared to a mesh interconnect, in which all cards are functional without a switch fabric, the star architecture may not be optimal from a cost-per-gigabit standpoint until fully populated by I/O cards. Alternatively, the star scheme may have a lower system cost since it is scalable and the same I/O cards can be used in a four-slot or larger system.
Connector slots
 FIGURE 1. Teradyne's VHDM L-Series connector optimizes cost and performance. |
Optimizing slot cost without sacrificing performance is easier with more low- and mid-performance products available to complement more costly leading edge, high-performance connectors (see Fig. 1). For example, open-pin field connectors, which fit on the same rear-organizing stiffener as higher-performing shielded versions, allow designers to create custom connector configurations that achieve specific performance needs and cost down targets. The ability to collocate any combination of connectors (high- to low-speed, single-ended, or differential) in a single module enables a mix of connections within the same slot.
Connector routing
Using the latest high-speed, high-density connectors allows flexible routing schemes that take up less space and can reduce layer count on the printed-circuit backplane. The PCB cost and board fabrication complexity, such as the fabrication of high-aspect-ratio plated through holes, are then significantly reduced. Both star and mesh architectures can achieve high layer-count reductions if the designer carefully lays out modular connectors in the early stages of the design.
A reduction of ten total layers on a 400-Gbit/s backplane saves hundreds of dollars. Cost-per-pin savings are insignificant compared to the cost savings of effective routing. Although high-performance connectors may not be the cheapest options, layer-count reduction (as much as 50% is possible) and subsequent PCB cost reduction can far outweigh incremental connector-pin cost.
This type of savings is exemplified in the following case study in which an OEM needed to design a chassis with a smaller footprint that consumed less rack space. To meet the customer's needs, a GbX connector was used in a dual-star, five-slot, 400-Gbit/s backplane that was highly optimized in only three signal layers. Using line cards on a 1.75 pitch with GbX 4-pair × 10 modules, the design took advantage of vertical routing channels, effectively reducing the number of layers by half and creating a new smaller product to complement a family of chassis that use the same I/O cards.
 FIGURE 2. Routing connectors vertically and horizontally can reduce PCB layer count. |
ViewDraw symbols and Allegro PCB footprints were used to develop the schematic and the PCB layout. Once the optimal spacing between each module was determined, the density and modularity of the connector created opportunities for saving routing layers. Traces were interleaved from the left and right so they flowed together into the space between the modules (see Fig. 2). To achieve that, the vertical size of the switch-fabric slot needed to be at least 15". In this arrangement, it was not necessary to duplicate the number of layers to route to another fabric position because traces from the left and right used the same copper layer. By avoiding extra layers to get to the second switch slot, the layer count was reduced from 20 to 10.
A vertical routing capability resulted in routing that is independent of the amount of space between slots and uses less space on the backplane. In this way, horizontally oriented cards reduce chassis height. Spaces between connectors preserve the use of wide lines, which reduces skin effect and lessens the need for equalization. Vertical routing also allows more flexibility in grouping positive and negative signals of a differential pair and reduces the number of schematic changes to finish the board. In this case, the optimal routing drove the final net list. Reduced layer count has the added benefit of improving performance by reducing the negative stub affects associated with thick backplanes.
Reducing PCB materials
Passive equalization, backdrilling, and new connector technology can also lower system-entry cost by avoiding the use of high-performance PCB materials. Typically, passive equalization and pre-emphasis improve signal integrity and extend the life of less expensive PCB materials such as FR4 in high-speed applications. Backdrilling boosts signal-channel data rates when layer count and PCB thickness is high and effectively reduces via stub effects related to thick boards, further pushing the performance capabilities of conventional board materials.
 FIGURE 3. Create islands of high-density to reduce PCB complexity and provide a system upgrade path. |
Significant cost reduction can also be achieved by designing separate, smaller, high-performance PCB assemblies that are then applied to the larger, more standard board using a mezzanine-type interconnect (see Fig. 3). Improved yields and reduced material cost can result. The design is highly scalable; multiple configurations easily enable varying amounts of performance. This is described as creating islands of high density. For example, co-planar and mezzanine connectors can be designed into a system to modularize high-performance subassemblies for use in multiple products. This strategy can increase PCB assembly yields, create scalability, and provide for future upgrade paths.
Using islands of high density, PCB assembly yields improve. Defects have less impact when costly components reside on a smaller PCB placed later in the system. When high speeds require the use of exotic PCB materials, mezzanine connectors allow smaller boards made of more expensive material to accommodate the high-speed signals, while the main PCB can use standard products such as FR4.
Scaling an existing design is another efficient way to cut cost. As OEMs seek performance improvements, connector suppliers have become sensitive to the need to lower system-design cost by scaling existing designs to their next-generation systems. The introduction of enhanced connector platforms that are backward-compatible with existing backplanes and daughtercards in the field, in combination with new silicon and daughtercard technology, enables next-generation system performance with minimal design and component selection cost.
Manufacturability
Reducing time-to-market and designing-in upgrade capability are also ways to increase return on investment. Some backplane system manufacturers can provide design and applications assistance based on their knowledge of product capabilities developed through the application of these products in the broader market. Often, they can provide tools that help make design tradeoffs faster, reducing design time and ensuring the optimal design.
"Design-For-Manufacturability" tools provide a framework to streamline the system-design cycle, allowing a sharper focus on perfecting the system design at its conceptual stage and therefore investing less time and money building prototypes. Evaluating the manufacturability of a system during the design cycle helps reduce delays down the line, often translating into significant cost savings on materials and labor as well as reduced time-to-market.
Striking an acceptable balance of performance, time-to-market, and cost requires far more attention to detail than ever before. Choices in connectors, board materials, and design approaches must be evaluated in terms of total entry cost and future scalability. As speeds increase, even marginally, the challenges in designing reliable high-performance systems grow exponentially, requiring innovative and integrated system design.
RICHARD HUMPHREY is product manager at Teradyne Connection Systems, 44 Simon St., Nashua, NH 03061. Tel: (603) 879-3106; email: rich.humphrey@teradyne.com.
